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low noise, low gain drift, g = 2000 instrumentation amplifier data sheet ad8428 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features fixed gain of 2000 access to internal nodes provides flexibility low noise: 1.5 nv/hz input voltage noise high accuracy dc performance gain drift: 10 ppm/c offset drift: 1 v/c gain accuracy: 0.2% cmrr: 130 db min excellent ac specifications bandwidth: 3.5 mhz slew rate: 40 v/s power supply range: 4 v to 18 v 8-pin soic package esd protection >5000 v (hbm) temperature range for specified performance: ?40c to +85c operational up to 125c applications sensor interface medical instrumentation patient monitoring functional block diagram + in ? in ? fi l +fil + v s ?v s ad8428 3k? 6k? 6k ? 6k? 6k ? 120k ? 120k ? 30.15 ? 3k? out ref 09731-001 figure 1. table 1. instrumentation amplifiers by category 1 general- purpose zero drift military grade low power low noise ad8220 ad8231 ad620 ad627 ad8428 ad8221 ad8290 ad621 ad623 ad8429 ad8222 ad8293 ad524 ad8235 ad8224 ad8553 ad526 ad8236 ad8228 ad8556 ad624 AD8426 ad8295 ad8557 ad8226 ad8227 1 see www.analog.com for the latest instrumentation amplifiers. general description the ad8428 is an ultralow noise instrumentation amplifier designed to accurately measure tiny, high speed signals. it delivers industry-leading gain accuracy, noise, and bandwidth. all gain setting resistors for the ad8428 are internal to the part and are precisely matched. care is taken in both the chip pinout and layout. this results in excellent gain drift and quick settling to the final gain value after the part is powered on. the high cmrr of the ad8428 prevents unwanted signals from corrupting the signal of interest. the pinout of the ad8428 is designed to avoid parasitic capacitance mismatches that can degrade cmrr at high frequencies. the ad8428 is one of the fastest instrumentation amplifiers available. the circuit architecture is designed for high bandwidth at high gain. the ad8428 uses a current feedback topology for the initial preamplifier gain stage of 200, followed by a difference amplifier stage of 10. this architecture results in a 3.5 mhz bandwidth at a gain of 2000 for an equivalent gain bandwidth product of 7 ghz. the ad8428 pinout allows access to internal nodes between the first and second stages. this feature can be useful for modifying the frequency response between the two amplification stages, thereby preventing unwanted signals from contaminating the output results. the performance of the ad8428 is specified over the industrial temperature range of ?40c to +85c. it is available in an 8-lead plastic soic package.
ad8428 data sheet rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? theory of operation ...................................................................... 13 ? architecture ................................................................................ 13 ? filter terminals ........................................................................... 13 ? reference terminal .................................................................... 13 ? input voltage range ................................................................... 14 ? layout .......................................................................................... 14 ? input bias current return path ............................................... 15 ? input protection ......................................................................... 15 ? radio frequency interference (rfi) ........................................ 16 ? calculating the noise of the input stage ................................. 16 ? outline dimensions ....................................................................... 18 ? ordering guide .......................................................................... 18 ? revision history 10/11revision 0: initial version
data sheet ad8428 rev. 0 | page 3 of 20 specifications v s = 15 v, v ref = 0 v, t a = 25c, g = 2000, r l = 10 k, unless otherwise noted. table 2. parameter test conditions/comments min typ max unit common-mode rejection ratio (rti) v cm = 10 v cmrr, dc to 60 hz 130 db cmrr at 50 khz 110 db noise (rti) v in +, v in ? = 0 v voltage noise f = 1 khz 1.3 1.5 nv/hz f = 0.1 hz to 10 hz 40 50 nv p-p current noise f = 1 khz 1.5 pa/hz f = 0.1 hz to 10 hz 150 pa p-p voltage offset input offset, v osi 100 v average tc t a = ?40c to +85c 1 v/c offset rti vs. supply (psrr) 120 db input current input bias current 200 na over temperature t a = ?40c to +85c 250 pa/c input offset current 50 na over temperature t a = ?40c to +85c 20 pa/c dynamic response ?3 db small signal bandwidth 3.5 mhz settling time to 0.01% 10 v step 0.75 s settling time to 0.001% 10 v step 1.4 s slew rate 40 50 v/s gain first stage gain 200 v/v subtractor stage gain 10 v/v total gain error v out = ?10 v to +10 v 0.2 % total gain nonlinearity v out = ?10 v to +10 v 5 ppm total gain vs. temperature 10 ppm/c input impedance (pin to ground) 1 1||2 g||pf input operating voltage range v s = 4 v to 18 v ?v s + 2.5 +v s ? 2.5 v over temperature t a = ?40c to +85c ?v s + 2.5 +v s ? 2.5 v output output swing r l = 2 k ?v s + 1.7 +v s ? 1.2 v over temperature t a = ?40c ?v s + 2.0 +v s ? 1.3 v t a = +85c ?v s + 1.6 +v s ? 1.1 v output swing r l = 10 k ?v s + 1.7 +v s ? 1.0 v over temperature t a = ?40c ?v s + 1.8 +v s ? 1.2 v t a = +85c ?v s + 1.4 +v s ? 0.9 v short-circuit current 30 ma reference input r in 132 k i in v in +, v in ? = 0 v 6.5 a voltage range ?v s +v s v reference gain to output 1 v/v reference gain error 0.01 %
ad8428 data sheet rev. 0 | page 4 of 20 parameter test conditions/comments min typ max unit filter terminals r in 2 6 k voltage range ?v s +v s v power supply operating range 4 18 v quiescent current 6.5 6.8 ma over temperature t a = ?40c to +85c 8 ma 1 the differential and common-mode input impedance s can be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 2 to calculate the actual impedance, see figure 1.
data sheet ad8428 rev. 0 | page 5 of 20 absolute maximum ratings table 3. parameter rating supply voltage 18 v output short-circuit current duration indefinite maximum voltage at ?in, +in 1 v s maximum voltage at ?fil, +fil v s differential input voltage 1 1 v maximum voltage at ref v s storage temperature range ?65c to +150c specified temperature range ?40c to +85c maximum junction temperature 140c esd human body model 5000 v charged device model 1250 v machine model 400 v 1 for voltages beyond these limits, us e input protection resistors. see the input protection section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package ja unit 8-lead soic_n 121 c/w esd caution
ad8428 data sheet rev. 0 | page 6 of 20 pin configuration and fu nction descriptions ?in 1 ?fil 2 +fil 3 +in 4 +v s 8 out 7 ref 6 ?v s 5 a d8428 top view (not to scale) 09731-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 ?in negative input terminal. 2 ?fil negative filter terminal. 3 +fil positive filter terminal. 4 +in positive input terminal. 5 ?v s negative power supply terminal. 6 ref reference voltage terminal. drive this terminal with a low impedance voltage source to level-shift the output. 7 out output terminal. 8 +v s positive power supply terminal.
data sheet ad8428 rev. 0 | page 7 of 20 typical performance characteristics t a = 25c, v s = 15 v, v ref = 0 v, r l = 10 k, unless otherwise noted. 1200 1000 800 600 400 200 0 ?40 ?20 40 20 0 hits v osi (v) 09731-003 n = 5170 mean = 2.12 sd = 7.332 figure 3. typical distribution of input offset voltage, v s = 5 v 1400 1200 1000 800 600 400 200 0 ?40 ?20 40 20 0 hits v osi (v) 09731-004 n = +5169 mean = ?2.57 sd = +7.31066 figure 4. typical distribution of input offset voltage, v s = 15 v 1400 1200 1000 800 600 400 200 0 ?3 ?2 ?1 3 12 0 hits v osi drift (v) 09731-005 n = 5166 mean = 0.398 sd = 0.42707 figure 5. typical distribution of input offset voltage drift 1600 1400 1200 1000 800 600 400 200 0 ?60 ?40 ?20 40 20 0 hits i bias (na) 09731-006 noninverting i bias inverting i bias n = +5171 mean = ?10.8 sd = +6.67496 n = +5171 mean = ?10.2 sd = +6.52901 figure 6. typical distributi on of input bias current 1000 800 600 400 200 0 ?8 ?6 ?4 6 04 2 ?2 hits i bias offset (na) 09731-007 n = +5171 mean = ?0.53 sd = +1.41655 figure 7. typical distribution of input bias current offset 1200 1000 800 600 400 200 0 ?600 ?400 200 400 0 ?200 hits gain error (v/v) 09731-008 n = +3487 mean = ?53.9 sd = +86.7774 figure 8. typical distribution of gain error, gain = 2000, v s = 15 v, r l = 10 k
ad8428 data sheet rev. 0 | page 8 of 20 15 10 5 0 ?15 ?10 ?5 ?15 ?10 ?5 0 5 10 15 input common-mode voltage (v) output voltage (v) 09731-009 v s = 15v v s = 12v v s = 5v figure 9. input common-mode voltage vs. output voltage, v s = 5 v, v s = 12 v, v s = 15 v 18 0 ?14 14 input bias current (na) common-mode voltage (v) 09731-010 2 4 6 8 10 12 14 16 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 ?11.8v +12v figure 10. input bias current vs. common-mode voltage, v s = 15 v 140 0 0.1 1 1m 100k 10k 1k 100 10 psrr (db) frequency (hz) 09731-011 20 40 60 80 100 120 +psrr ?psrr figure 11. psrr vs. frequency 72 ?12 100 1k 10k 100k 100m 1m 10m gain (db) frequency (hz) 09731-014 ?6 0 6 12 18 24 30 36 42 48 54 60 66 figure 12. gain vs. frequency 170 80 1 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) 09731-015 90 100 gain = 2000 110 120 130 140 150 160 figure 13. cmrr vs. frequency 120 0 1 10 100 1k 10k 100k 1m cmrr (db) frequency (hz) 09731-016 10 20 30 40 50 60 70 80 90 100 110 gain = 2000 figure 14. cmrr vs. frequency, 1 k source imbalance
data sheet ad8428 rev. 0 | page 9 of 20 5 ?2 0 120 change in input offset voltage (v) warm-up time (seconds) 09731-017 ?1 0 1 2 3 4 10 20 30 40 50 60 70 80 90 100 110 figure 15. change in input offset voltage (v osi ) vs. warm-up time 15 ?30 ?25 ?20 ?2.4 1.2 ?40 125 input bias current (na) input offset current (na) temperature (c) 09731-018 ?25?105 203550658095110 0.8 0.4 0 ?0.4 ?0.8 ?1.2 ?1.6 ?2.0 ?15 ?10 0 5 ?5 10 ib+ ib? ios normalized at 25c figure 16. input bias current and input offset current vs. temperature 250 ?200 ?40 125 gain error (v/v) temperature (c) 09731-019 ?150 ?100 ?50 0 50 100 150 200 ?25?105 203550658095110 representative data normalized at 25c figure 17. gain error vs. temperature, normalized at 25c 70 ?30 ?40 125 cmrr (nv/v) temperature (c) 09731-020 ?25?105 203550658095110 representative data normalized at 25c ?20 ?10 0 10 20 30 40 50 60 figure 18. cmrr vs. temperature, normalized at 25c 9.0 8.5 8.0 7.5 5.0 5.5 6.0 6.5 7.0 ?40 125 supply current (ma) temperature (c) 09731-021 ?25?105 203550658095110 figure 19. supply current vs. temperature 50 ?50 ?40 125 short-circuit current (ma) temperature (c) 09731-022 ?25?105 203550658095110 ?20 ?30 ?40 ?10 0 10 20 30 40 i short+ i short? figure 20. short-circuit current vs. temperature
ad8428 data sheet rev. 0 | page 10 of 20 100 0 ?40 125 slew rate (v/s) temperature (c) 09731-023 10 20 30 40 50 60 70 80 90 ?25?105 203550658095110 +sr ?sr figure 21. slew rate vs. temperature, v s = 15 v 100 0 ?40 125 slew rate (v/s) temperature (c) 09731-024 10 20 30 40 50 60 70 80 90 ?25?105 203550658095110 +sr ?sr figure 22. slew rate vs. temperature, v s = 5 v + v s ?0.5 +0.5 ?1.0 +1.0 ?1.5 ?2.0 ?2.5 +1.5 +2.0 +2.5 ?v s 46810 18 16 14 12 input voltage (v) referred to supply voltages supply voltage (v s ) 09731-025 ?40c +25c +85c +125c figure 23. input voltage limit vs. supply voltage + v s ?v s 4 supply voltage (v s ) 09731-026 56789101112131415 17 16 ?0.4 ?0.8 ?1.2 +0.4 +0.8 +1.2 +1.6 +2.0 output voltage swing (v) referred to supply voltages ?40c +25c +85c +125c figure 24. output voltage swing vs. supply voltage, r l = 10 k + v s ?v s 4 supply voltage (v s ) 09731-027 5 6 7 8 9 10 11 12 13 14 15 1716 ?0.4 ?0.8 ?1.2 +0.4 +0.8 +1.2 +1.6 +2.0 output voltage swing (v) referred to supply voltages ?40c +25c +85c +125c figure 25. output voltage swing vs. supply voltage, r l = 2 k 15 0 ?15 ?10 ?5 5 10 100 1k 10k 100k output voltage swing (v) load ( ? ) 09731-028 ?40c +25c +85c +125c figure 26. output voltage swing vs. load resistance, v s = 15 v
data sheet ad8428 rev. 0 | page 11 of 20 + v s ?0.5 +0.5 ?1.0 +1.0 ?1.5 +1.5 ?v s 0.01 0.1 1 10 output voltage swing (v) referred to supply voltages output current (ma) 09731-029 ?40c +25c +85c +125c figure 27. output voltage swing vs. output current, v s = 15 v 20 15 10 5 0 ?20 ?15 ?10 ?5 ?10?8?6?4?2 0 2 4 6 10 8 gain nonlinearity (5 ppm/div) output voltage (v) 09731-030 gain = 2000 figure 28. gain nonlinearity, r l = 10 k 100 0.1 1 10 0.1 1 10 100 1k 10k 100k noise (nv/ hz) frequency (hz) 09731-031 gain = 2000 figure 29. rti voltage noise spectral density vs. frequency 09731-032 20nv/div 1s/div figure 30. 0.1 hz to 10 hz rti voltage noise 16 1 1 10 100 1k 10k 100k noise (pa/ hz) frequency (hz) 09731-033 2 3 4 5 6 7 8 9 10 11 12 13 14 15 figure 31. current noise spectral density vs. frequency 09731-034 50pa/div 1s/div figure 32. 0.1 hz to 10 hz current noise
ad8428 data sheet rev. 0 | page 12 of 20 09731-035 1s/div 0.002%/div 5v/div 752ns to 0.01% 1408ns to 0.001% time (s) figure 33. large signal pulse response and settling time, 10 v step, v s = 15 v 09731-036 20mv/div 1s/div gain = 2000 figure 34. small signal pulse response, r l = 10 k, c l = 100 pf 09731-037 50mv/div 1s/div no load c l = 500pf c l = 770pf figure 35. small signal pulse response with various capacitive loads, no resistive load 1800 0 2 4 6 8 101214161820 settling time (ns) step size (v) 09731-038 200 400 600 800 1000 1200 1400 1600 settled to 0.001% settled to 0.01% figure 36. settling time vs. step size
data sheet ad8428 rev. 0 | page 13 of 20 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ?in ?rg ref out node 1 node 2 ii +rg r2 3k? r1 3k ? 30.15 ? +v s v b ?v s +v s +v s +v s +v s ?v s ?v s ?v s +v s ?v s ?v s 4 2 3 1 7 6 i b compensation i b c ompensation r3 6k? r5 6k? r4 6k? r6 6k? ?fil +fil 120k ? r7 120k ? r8 09731-042 r g figure 37. simplified schematic architecture the ad8428 is based on the classic 3-op-amp topology. this topology has two stages: a gain stage (preamplifier) to provide differential amplification by a factor of 200, followed by a differ- ence amplifier stage to remove the common-mode voltage and provide additional amplification by a factor of 10. figure 37 shows a simplified schematic of the ad8428. the first stage works as follows. to keep its two inputs matched, amplifier a1 must keep the collector of q1 at a constant voltage. it does this by forcing ?rg to be a precise diode drop from ?in. similarly, a2 forces +rg to be a constant diode drop from +in. therefore, a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows across this resistance must also flow through the r1 and r2 resistors, creat- ing a gained differential signal between the a2 and a1 outputs. the second stage is a g = 10 difference amplifier, composed of amplifier a3 and resistors r3 through r8. this stage removes the common-mode signal from the amplified differential signal. the transfer function of the ad8428 is v out = 2000 ( v in+ ? v in? ) + v ref filter terminals the ?fil and +fil terminals allow access between r3 and r4, and between r5 and r6, respectively. adding a filter between these two terminals modifies the signal gain vs. frequency before it reaches the second amplifier stage. reference terminal the output voltage of the ad8428 is developed with respect to the potential on the reference terminal. this is useful when the output signal must be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level- shift the output so that the ad8428 can drive a single-supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s . for best performance, the source impedance to the ref terminal should be kept well below 1 . as shown in figure 37 , the reference terminal, ref, is at one end of a 120 k resistor. additional impedance at the ref terminal adds to this 120 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be calculated as follows: 2 (120 k + r ref )/(240 k + r ref ) only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades the cmrr of the amplifier. incorrect v correct ad8428 op1177 + ? v ref ad8428 ref 09731-043 figure 38. driving the reference pin
ad8428 data sheet rev. 0 | page 14 of 20 input voltage range the 3-op-amp architecture of the ad8428 applies gain in the first stage before removing the common-mode voltage in the difference amplifier stage. internal nodes between the first and second stages (node 1 and node 2 in figure 37 ) experience a combination of an amplified differential signal, a common-mode signal, and a diode drop. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. figure 9 shows the allowable input common-mode voltage ranges for various output voltages and supply voltages. layout to ensure optimum performance of the ad8428 at the pcb level, care must be taken in the design of the board layout. the pins of the ad8428 are especially arranged to simplify board layout and to help minimize parasitic imbalance between the inputs. ?in 1 ?fil 2 +fil 3 +in 4 +v s 8 out 7 ref 6 ?v s 5 ad8428 top view (not to scale) 09731-044 figure 39. pinout diagram common-mode rejection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to maintain high cmrr over frequency, the input source impedance and capacitance of each path should be closely matched. additional source resistance in the input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the inputs with parasitic capacitance from the pcb traces. parasitic capacitance at the filter pins can also affect cmrr over frequency. if the board design has a component at the filter pins, the component should be chosen so that the parasitic capacitance is as small as possible. power supplies and grounding use a stable dc voltage to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. see the psrr performance curves in figure 11 for more information. place a 0.1 f capacitor as close as possible to each supply pin. because the length of the bypass capacitor leads is critical at high frequency, surface-mount capacitors are recommended. a parasitic inductance in the bypass ground trace works against the low impedance created by the bypass capacitor. as shown in figure 40 , a 10 f capacitor can be used farther away from the device. for larger value capacitors, which are intended to be effective at lower frequencies, the current return path distance is less critical. in most cases, the 10 f capacitor can be shared by other precision integrated circuits. ad8428 + v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s v out 09731-045 figure 40. supply decoupling, ref, and output referred to local ground a ground plane layer is helpful to reduce undesired parasitic inductances and to minimize voltage drops with changes in current. the area of the current path is directly proportional to the magnitude of parasitic inductances and, therefore, the impedance of the path at high frequency. large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into the amplifier inputs. because load currents flow from the supplies, the load should be connected at the same physical location as the bypass capac- itor grounds. reference pin the output voltage of the ad8428 is developed with respect to the potential on the reference terminal. ensure that ref is tied to the appropriate local ground.
data sheet ad8428 rev. 0 | page 15 of 20 input bias current return path the input bias current of the ad8428 must have a return path to ground. when the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown in figure 41 . thermocouple +v s ref ?v s ad8428 capacitively coupled +v s ref c c ?v s ad8428 transformer +v s ref ?v s ad8428 incorrect capacitively coupled +v s ref c r r c ?v s ad8428 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? ad8428 transformer +v s ref ?v s ad8428 correct 09731-046 figure 41. creating an inpu t bias current return path input protection do not allow the inputs of the ad8428 to exceed the ratings stated in the absolute maximum ratings section. if these ratings cannot be adhered to, add protection circuitry in front of the ad8428 to limit the maximum current into the inputs (see the i max section). i max the maximum current into the ad8428 inputs, i max , depends on time and temperature. at room temperature, the device can withstand a current of 10 ma for at least one day. this time is cumulative over the life of the device. input voltages beyond the rails if voltages beyond the rails are expected, use an external resistor in series with each input to limit current during overload condi- tions. the limiting resistor at each input can be computed using the following equation: max suppl in protect i vv r ? noise sensitive applications may require a lower protection resistance. low leakage diode clamps, such as the bav199, can be used at the inputs to shunt current away from the ad8428 inputs and, therefore, allow smaller protection resistor values. to ensure that current flows primarily through the external protection diodes, place a small value resistor, such as a 33 resistor, between the diodes and the ad8428. simple method low noise method +v s ad8428 r protect r protect ?v s i v in+ + ? v in? + ? +v s + v s ad8428 r protect 33? 33? r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s 09731-047 figure 42. protection for voltages beyond the rails large differential input voltage at high gain if large differential voltages at high gain are expected, use an external resistor in series with each input to limit current during overload conditions. the limiting resistor at each input can be computed using the following equation: ? ? ? ? ? ? ? ? ? ? v1 2 1 noise sensitive applications may require a lower protection resistance. low leakage diode clamps, such as the bav199, can be used across the ad8428 inputs to shunt current away from the inputs and, therefore, allow smaller protection resistor values. ad8428 r protect r protect i v diff + ? 09731-048 figure 43. protection for large differential voltages
ad8428 data sheet rev. 0 | page 16 of 20 radio frequency interference (rfi) because of its high gain and low noise properties, the ad8428 is a highly sensitive amplifier. therefore, rf rectification can be a problem if the ad8428 is used in applications that have strong rf signal sources present. the problem is intensified if long leads or pcb traces are required to connect the amplifier to the signal source. the disturbance can appear as a dc offset voltage or a train of pulses. high frequency signals can be filtered with a low-pass filter network at the input of the instrumentation amplifier, as shown in figure 44 . r r ad8428 + v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s c d 10nf c c 1nf c c 1nf 33? 33? 09731-049 l* l* *chip ferrite bead. figure 44. rfi suppression the filter limits both the differential and common-mode band- width, as shown in the following equations: )2(2 1 c d diff ccr uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c . c d affects the differential signal, and c c affects the common- mode signal. choose values of r and c c that minimize rfi. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the ad8428 . by using a value of c d one order of magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved. resistors add noise; therefore, the choice of resistor and capac- itor values depends on the desired trade-off between noise, input impedance at high frequencies, and rfi immunity. to achieve low noise and sufficient rfi filtering, the use of inductive ferrite beads is recommended (see figure 44 ). using inductive ferrite beads allows the value of the resistors to be reduced, which helps to minimize the noise at the input. for best results, place the rfi filter network as close as possible to the amplifier. layout is critical to ensure that rf signals are not picked up on the traces after the filter. if rf interference is too strong to be filtered, shielding is recommended. note that the resistors used for the rfi filter can be the same as those used for input protection (see the input protection section). calculating the noise of the input stage the total noise of the amplifier front end depends on much more than the specifications in this data sheet. the three main contributors to noise are as follows: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. in the following calculations, noise is referred to the input (rti); that is, all sources of noise are calculated as if the source appeared at the amplifier input. to calculate the noise referred to the ampli- fier output (rto), simply multiply the rti noise by the gain of the instrumentation amplifier. source resistance noise any sensor connected to the ad8428 has some output resistance. there may also be resistance placed in series with the inputs for protection from either overvoltage or radio frequency interference. this combined resistance is labeled r1 and r2 in figure 45 . any resistor, no matter how well made, has an intrinsic level of noise. this noise is proportional to the square root of the resistor value. at room temperature, the value is approximately equal to 4 nv/hz (resistor value in k). r2 r1 senso r ad8428 09731-050 figure 45. source resistance from sensor and protection resistors for example, assuming that the combined sensor and protec- tion resistance is 4 k on the positive input and 1 k on the negative input, the total noise from the input resistance is ( ) ( ) hznv/9.816641444 2 2 =+=+
data sheet ad8428 rev. 0 | page 17 of 20 voltage noise of the instrumentation amplifier total noise density calculation unlike other instrumentation amplifiers in which an external resistor is used to set the gain, the voltage noise specification of the ad8428 already includes the input noise, output noise, and the r g resistor noise. to determine the total noise of the in-amp, referred to input, combine the source resistance noise, voltage noise, and current noise contribution by the sum of squares method. for example, if the r1 source resistance in figure 45 is 4 k and the r2 source resistance is 1 k, the total noise, referred to input, is current noise of the in strumentation amplifier the contribution of current noise to the input stage in nv/hz is calculated by multiplying the source resistance in k by the specified current noise of the instrumentation amplifier in pa/hz. hznv/0.112.65.19.8 222 =++ for example, if the r1 source resistance in figure 45 is 4 k and the r2 source resistance is 1 k, the total effect from the current noise is calculated as follows: ()() hznv/2.65.115.14 2 2 =+
ad8428 data sheet rev. 0 | page 18 of 20 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 46. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ad8428arz ?40c to +125c 8-lead soic_n r-8 ad8428arz-rl ?40c to +125c 8-lead soic_n, 13 tape and reel r-8 1 z = rohs compliant part.
data sheet ad8428 rev. 0 | page 19 of 20 notes
ad8428 data sheet rev. 0 | page 20 of 20 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09731-0-10/11(0)

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